Different scan compression techniques have emerged for compressing scan data patterns, generated using automatic test-pattern generation (ATPG) tools, for reducing both test application time and test data volume. Current scan compression techniques rely on inserting a decompressor between a limited number of compressed scan inputs and a large number of internal scan chains. The decompressor can be designed as a combinational circuit that generates decompressed scan data patterns for the internal scan chains depending on the compressed scan data patterns applied to the compressed scan inputs, or as a sequential circuit that can be used to generate the decompressed scan data patterns for the internal scan chains based on previously stored states of the sequential elements.
The following U.S. Patent Documents and other publications listed below are incorporated by reference.    U.S. Patent Documents
6,327,687Dec. 1, 2001Rajski et al6,611,933August 2003Koenemann et al20030154433August 2003Wang et alOther Publications    K.-J. Lee et al, “Broadcasting Test Patterns to Multiple Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 12, pp. 1793–1802, December 1999.    A. R. Pandey et al, “An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs,” Proc., IEEE 2002 Design, Automation and Test in Europe (DATE), pp. 368–375–2002.    B. Koenemann, “LFSR-Coded Test Patterns for Scan Designs”, Proc., European Test Conf., pp. 237–242, 1991.
Scan compression techniques utilizing a combinational decompressor typically consist of an exclusive-OR (XOR) or multiplexor (MUX) tree that may be controlled by additional control inputs or controlled by an internally stored state. See the patent co-authored by Koenemann et al. (2003) and the patent application co-authored by Wang et al. (2003). Scan compression techniques utilizing a sequential decompressor typically embed a linear-feedback shift register (LFSR) between the compressed scan inputs and internal scan chains and use the compressed scan inputs to control the LFSR in a way that makes it generate the required decompressed scan data patterns, while utilizing ‘don't care’ states present in the decompressed scan data patterns to reduce the complexity of the problem. See the paper co-authored by Koenemann et al. (1991) and the patent co-authored by Rajski et al. (2001).
In general, scan compression techniques utilizing a sequential decompressor such as an LFSR circuit are difficult to use, requiring additional software to solve the linear equations involved in order to translate the decompressed scan data patterns into the external compressed scan data patterns that can be used to generate the required decompressed scan data patterns through the LFSR. In some cases, these linear equations can turn out to be unsolvable, requiring multiple iterative runs where the decompressed scan data patterns are reordered, duplicated, or regenerated in order to be able to generate compressed scan data patterns which covers all the required faults. This can result in a significant computational overhead. In general, the compression capability of these techniques is limited since it requires that the decompressed scan data patterns be generated loosely in order to guarantee that the compression equations can be solved. This results in compressing decompressed scan data patterns that are sub-optimal, as opposed to compressing tightly packed decompressed scan data patterns where both static and dynamic compaction are performed aggressively. Finally, any changes made to the circuit after generating the decompressed scan data patterns require abandoning these patterns and going back to the beginning of the iterative process. This makes these techniques much less attractive than techniques utilizing a combinational decompressor, built mainly out of XOR or MUX gates.
Current techniques utilizing a combinational decompressor, such as circuits built out of XOR or MUX gates, utilize different combinational circuit designs for generating the decompressed scan data patterns. In some techniques, the decompressed scan data patterns are generated such that the decompressed scan data patterns for each internal scan chain depends on multiple compressed scan inputs. In other techniques, the decompressed scan data patterns for each internal scan chain depends on only one compressed scan input, with a few additional control inputs used to alter the relationship for different scan patterns. Finally, in some techniques, sequential elements are used in place of the additional control inputs to alter the relationship for different scan patterns. These sequential elements are typically preloaded with different data for each scan pattern. The advantage of these techniques is that the relationship between the decompressed scan data patterns and the compressed scan data patterns is easy to define and understand, and can be easily incorporated into the ATPG tools as part of the vector generation process, such that the compressed scan data patterns are generated automatically, with dynamic compaction being aggressively applied.
The main difficulty with current decompression solutions utilizing a combinational decompressor is that the decompression is typically done in one stage, which is placed between the compressed scan inputs and the first scan cell of each internal scan chains. This introduces a long combinational path between the compressed scan inputs and the internal scan cells, which slows down the speed at which the scan chains can be operated. For example, a design including 8 compressed scan inputs and 512 internal scan chains (1 to 64 ratio) requires 6 levels of XOR gates, XOR gates being among the slowest combinational logic library cells. An additional delay is further introduced due to the fact that the first scan cell is typically located at a distance from the compressed scan inputs. Finally, since the compressed scan inputs are typically shared in normal mode, this can result in overloading the input pins and reducing the amount of time these pins can be operated at, which can adversely affect the regular chip functionality. The same problems exist in combinational decompressors utilizing MUX gates as their basic building block.
A similar problem exists when the scan data responses captured in the internal scan chains are compressed into compressed scan data responses driven out on a smaller number of compressed scan outputs. For compression techniques utilizing a sequential compressor, difficulties arise due to the fact that all unknowns now have to be accounted for and tolerated in scan mode (during shift-in and shift-out operations), which can result in a significant gate overhead for scan designs utilizing these techniques. For designs utilizing a combinational compressor, a similar number of XOR gate levels may have to be placed between the last scan cell of the internal scan chains and the compressed scan outputs, creating similar delays and loading problems as the combinational decompressor used on the input side. The same problems also exist in combinational compressor designs utilizing MUX gates as their basic building block.
Accordingly, there is a need to develop an improved method and apparatus for scan compression. The method we propose in this invention is based on using two or more decompressors and two or more compressors, and placing them in between the scan cells of the scan-based design.